A 60 GHz LNA with 18.6 dB gain and 5.7 dB NF in 90nm CMOS

A 60 GHz low noise amplifier is implemented in a commercial 90 nm RF CMOS process. A scalable model based on electromagnetic simulation is adopted to model on-chip microstrip transmission lines. First-pass silicon success has been achieved by accurate modeling of passive and active devices and careful layout. The three-stage LNA achieves 18.6 dB gain, a noise figure of 5.7 dB and an input P_1dB of -14.8 dBm. It consumes 24 mA from a 1.2 V supply. The total LNA die area with pads is 1.4 × 0.5 mm².