A 60 GHz LNA with 18.6 dB gain and 5.7 dB NF in 90nm CMOS

Author

Kang, Kai ; Brinkhoff, James ; Lin, Fujiang

Author_Institution

Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore

fYear

2010

fDate

8-11 May 2010

Firstpage

164

Lastpage

167

Abstract

A 60 GHz low noise amplifier is implemented in a commercial 90 nm RF CMOS process. A scalable model based on electromagnetic simulation is adopted to model on-chip microstrip transmission lines. First-pass silicon success has been achieved by accurate modeling of passive and active devices and careful layout. The three-stage LNA achieves 18.6 dB gain, a noise figure of 5.7 dB and an input P_1dB of -14.8 dBm. It consumes 24 mA from a 1.2 V supply. The total LNA die area with pads is 1.4 × 0.5 mm².

Keywords

CMOS integrated circuits; low noise amplifiers; microstrip lines; RF CMOS process; electromagnetic simulation; frequency 60 GHz; gain 18.6 dB; low noise amplifier; noise figure 5.7 dB; on-chip microstrip transmission lines; size 90 nm; CMOS process; Electromagnetic modeling; Gain; Low-noise amplifiers; Microstrip; Noise measurement; Radio frequency; Radiofrequency amplifiers; Semiconductor device modeling; Transmission lines; CMOS; low noise amplifier; microstrip; millimeter wave;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave and Millimeter Wave Technology (ICMMT), 2010 International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-5705-2

Type

conf

DOI

10.1109/ICMMT.2010.5525259

Filename

5525259