Title :
Fault characterizations and design-for-testability technique for detecting IDDQ faults in CMOS/BiCMOS circuits
Author :
Raahemifar, Kaamran ; Ahmadi, Majid
Author_Institution :
Electr. & Comput. Eng. Dept., Ryerson Polytech. Univ., Toronto, Ont., Canada
Abstract :
This paper provides the results of a simulation-based fault characterization study of CMOS/BiCMOS logic families. We show that most of the shorts cause IDDQ faults, while open defects result in delay or stuck-open faults. We propose a design-for-testability technique for detecting short and bridging faults in CMOS/BiCMOS logic circuits. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated
Keywords :
BiCMOS logic circuits; CMOS logic circuits; VLSI; delays; design for testability; fault diagnosis; integrated circuit testing; CMOS/BiCMOS logic circuits; CMOS/BiCMOS logic families; VLSI; bridging fault; circuit modification; delay faults; design-for-testability; fault detection; normal mode behavior; open defects; short fault; simulation-based fault characterization; stuck-open faults; BiCMOS integrated circuits; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Current supplies; Delay; Electrical fault detection; Fault detection; Power supplies;
Conference_Titel :
Electrical and Computer Engineering, 2001. Canadian Conference on
Conference_Location :
Toronto, Ont.
Print_ISBN :
0-7803-6715-4
DOI :
10.1109/CCECE.2001.933594
