• DocumentCode
    3238266
  • Title

    A robust model parameter extraction technique based on meta-evolutionary programming for high speed/high frequency package interconnects

  • Author

    Damavandi, Nader ; Safavi-Naeini, Safieddin

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
  • Volume
    2
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    1151
  • Abstract
    A high efficiency version of the evolutionary algorithm called meta-evolutionary programming (meta-EP) is proposed for extraction of the circuit model parameters of the basic structures in the complex high speed/high frequency package interconnects such as flip chip interconnects. The algorithm is integrated with a diversity enhancement method called niching in order to decrease the chance of premature convergence. The method is applied to model parameter extraction of some flip chip interconnects such as coplanar waveguide (CPW) and stripline transitions in multi-layered structures. The results of this parametric modeling in all cases show excellent success with high accuracy in a wide range of frequency up to 50 GHz. Comparison with results, achieved from other techniques in these cases, proves the robustness of the proposed method
  • Keywords
    coplanar waveguides; evolutionary computation; feature extraction; flip-chip devices; high-speed integrated circuits; integrated circuit interconnections; integrated circuit packaging; network parameters; strip line transitions; waveguide transitions; CPW-CPW transition; HF package interconnects; circuit model parameters; convergence; coplanar waveguide transition; diversity enhancement method; evolutionary algorithm; flip chip interconnects; high speed/high frequency package interconnects; meta-EP; meta-evolutionary programming; multi-layered structures; niching; parametric modeling; robust model parameter extraction; stripline transition; Coplanar waveguides; Diversity methods; Evolutionary computation; Flip chip; Frequency; Genetic programming; Integrated circuit interconnections; Packaging; Parameter extraction; Robustness;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical and Computer Engineering, 2001. Canadian Conference on
  • Conference_Location
    Toronto, Ont.
  • ISSN
    0840-7789
  • Print_ISBN
    0-7803-6715-4
  • Type

    conf

  • DOI
    10.1109/CCECE.2001.933604
  • Filename
    933604