On high speed add-compare-select for Viterbi decoders

Author

Pillai, R.V.K. ; Arcy, Paul D.

Author_Institution

StarCore Technol. Centre, Agere Syst., Atlanta, GA, USA

Volume

2

fYear

2001

fDate

2001

Firstpage

1193

Abstract

Add-compare-select (ACS) operations form the kernel of Viterbi algorithms. Owing to the ostensibly sequential nature of the ACS algorithm, hardware implementations often used to be slower. We propose a concurrent add-compare scheme that completes addition and comparison almost simultaneously. Power delay models that reflect the algorithmic, circuit and technological limitations of the target realization are developed. With radix 2 and 4 ACSs involving 16 bit operands, the proposed schemes offer a worst case delay reduction of better than 10% for sub 0.2 micron CMOS processes

Keywords

CMOS logic circuits; VLSI; Viterbi decoding; adders; delays; digital arithmetic; 0.2 mum; 16 bit; ACS algorithm; CMOS process; Viterbi algorithms; Viterbi decoders; concurrent add-compare scheme; digital signal processing; hardware implementation; high speed add-compare-select; power delay models; worst case delay reduction; CMOS technology; Circuits; Decoding; Delay; Digital signal processing; Hardware; Kernel; Semiconductor device modeling; Throughput; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2001. Canadian Conference on

Conference_Location

Toronto, Ont.

ISSN

0840-7789

Print_ISBN

0-7803-6715-4

Type

conf

DOI

10.1109/CCECE.2001.933611

Filename

933611