3-D effect of cell designs on the breakdown voltage of power SOI-LDMOS

Summary form only given. Dielectric isolation technology using Silicon on Insulator (SOI) substrates has attracted much attention in smart power ICs because of inherently superior isolation. In integrating power devices with control electronics on the same chip as smart power ICs, it is desirable to minimize the area of power device region while maximizing the performances (i.e., high breakdown voltage and low on-resistance), since the area of power device region mainly determines the total chip size and hence the cost. Recent publications have shown that lateral SOI power devices can achieve high breakdown voltage by optimizing the two dimensional (2-D) device parameters in accordance with the RESURF principle. However, in practice, it is also necessary to optimize the three dimensional (3-D) device parameters in order to support a given breakdown voltage within the smallest area. In this paper, we report the effect of 3-D parameters such as the curvatures of the drain and source regions, on the breakdown voltages of lateral DMOSFET (LDMOS) in SOI substrates based on experimental results and numerical simulations using cylindrical coordinates with the device simulator MEDICI