• DocumentCode
    3238843
  • Title

    Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing

  • Author

    Sinanoglu, Ozgur ; Marinissen, Erik Jan

  • Author_Institution
    Dept. of Math & Comput. Sci., Kuwait Univ., Safat
  • fYear
    2008
  • fDate
    10-14 March 2008
  • Firstpage
    182
  • Lastpage
    187
  • Abstract
    Modular SOC testing offers numerous benefits that include test power reduction, ease of timing closure, and test re-use among many others. While all these benefits have been emphasized by researchers, the test time and data volume comparisons has been mostly constrained within the context of modular SOC testing only, by comparing the impact of various different modular SOC testing techniques to each other. In this paper, we provide a theoretical test data volume analysis that compares the monolithic test of a flattened design with the same design tested in a modular manner; we present numerous experiments that gauge the magnitude of this benefit. We show that the test data volume reduction delivered by modular SOC testing directly hinges on the test pattern count variation across different modules, and that this reduction can exceed 99% in the SOC benchmarks that we have experimented with.
  • Keywords
    integrated circuit testing; system-on-chip; flattened design; modular SOC testing; monolithic test; test data volume analysis; Automatic test pattern generation; Benchmark testing; Computer science; Data analysis; Energy consumption; Fasteners; Investments; Semiconductor device testing; Technological innovation; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe, 2008. DATE '08
  • Conference_Location
    Munich
  • Print_ISBN
    978-3-9810801-3-1
  • Electronic_ISBN
    978-3-9810801-4-8
  • Type

    conf

  • DOI
    10.1109/DATE.2008.4484683
  • Filename
    4484683