Floating-body concerns for SOI dynamic random access memory (DRAM)

Summary form only given. As operating voltages are reduced it becomes increasingly challenging to write a usable signal into the DRAM storage capacitor because of the nonscalability of threshold voltage, due to the limiting effects of subthreshold slope and substrate sensitivity. Since the maximum wordline voltage is limited by reliability considerations, it is extremely important that the threshold voltage of the DRAM array MOSFET be made as low as possible while meeting the static off-current objective for charge retention. SOI, compared to bulk CMOS, appears attractive for a low-voltage (<2 V) DRAM because its superior subthreshold slope and low substrate sensitivity yield a lower source-follower threshold voltage, resulting in increased logical 1 level to be written for the same operating conditions. However, transient effects of the floating body must be considered when designing for long data retention time and low active power. Although earlier work has considered dynamic retention problems for SOI DRAM during normal read/write operations, simulation results presented in this paper address a transient SOI DRAM leakage mechanism which appears during page mode operation, for both partially and fully depleted designs. Two novel solutions for suppressing the transient leakage mechanism have been investigated