An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers

Low-cost test methodologies for systems-on-chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in order to guarantee high test quality, while minimizing application costs. Consequently, low-cost test strategies can be run on testers offering lower performance and/or reduced features with respect to traditional automatic test equipments (ATEs); these equipments are usually referred to as low-cost testers. This paper proposes a methodology for reducing the test data volume for the application of SoC low-cost test procedures. The method exploits a tester architecture organization suitable for SoCs testing, which includes a programmable device: the usage of this configurable block joined to the analysis of test pattern regularities permits minimizing the test data volume, thus improving the tester capabilities. The proposed method relies on test pattern compression at system level and it does not address core level pattern manipulation, as several other previously published works do. Case studies are proposed, which provide data about the application of the proposed methodology to the test of SoCs including self-testable processor and memory cores. IEEE 1149.1 and IEEE 1500 test access mechanisms are considered. The achieved pattern depth reduction ratio is up to about the 64% for the considered case studies.