Floating-body effects on propagation delay in SOI/CMOS LSIs

Author

Ueda, K. ; Morinaka, H. ; Yamaguchi, Y. ; Iwamatsu, T. ; Kim, I.J. ; Inuoue, Y. ; Mashiko, K. ; Sumi, T.

Author_Institution

Syst. LSI Lab., Mitsubishi Electr. Corp., Itami, Japan

fYear

1996

fDate

30 Sep-3 Oct 1996

Firstpage

142

Lastpage

143

Abstract

Summary form only given. The analyses of floating body instabilities in partially-depleted SOI/CMOS devices have been carried out using simulations and transistor measurements. To date, however, these analyses have been limited to small scale ICs. Thus, the applicability of partially-depleted SOI/CMOS devices with floating-body configurations to VLSI chips has not been clarified yet. This paper analyzes the frequency-dependent delay time of a 0.5 μm 64-bit adder under various supply voltages and temperatures together with the body potential of floating-body devices using a high-accuracy device simulator

Keywords

CMOS logic circuits; adders; circuit stability; delays; integrated circuit modelling; large scale integration; silicon-on-insulator; 0.5 micron; 64 bit; SOI/CMOS LSI; Si; VLSI chips; adder; body potential; floating body instability; frequency-dependent delay time; high-accuracy device simulator; partially-depleted SOI/CMOS devices; propagation delay; supply voltages; temperatures; Added delay; Adders; Analytical models; Delay effects; Frequency; Laboratories; Large scale integration; Propagation delay; Temperature; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1996. Proceedings., 1996 IEEE International

Conference_Location

Sanibel Island, FL

ISSN

1078-621X

Print_ISBN

0-7803-3315-2

Type

conf

DOI

10.1109/SOI.1996.552534

Filename

552534