• DocumentCode
    3238949
  • Title

    Parasitic bipolar turn-on of PD-SOI MOSFETs in dynamic logic circuits

  • Author

    Chin, Steven C. ; Tseng, Ying-Che ; Woo, Jason C S

  • Author_Institution
    Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
  • fYear
    1996
  • fDate
    30 Sep-3 Oct 1996
  • Firstpage
    144
  • Lastpage
    145
  • Abstract
    Due to its reduction in junction capacitance, increased current drive, and higher transconductance, SOI is very well suited to applications in high-speed digital logic circuits. Coupled with the common practice of utilizing dynamic logic in critical circuit pathways, one should expect SOI to have a very large impact on speeding up circuit blocks if it is applied to dynamic logic. Specifically, PD-SOI would be a better candidate as opposed to FD-SOI as it has better threshold control. However, this work will report for the first time erroneous operation of PD-SOI dynamic logic circuits resulting from the floating body induced turn-on of the parasitic bipolar transistor. In addition, potential solutions to overcome this unwanted bipolar leakage of stored charge will also be presented
  • Keywords
    MOS logic circuits; silicon-on-insulator; PD-SOI MOSFET; charge leakage; dynamic logic circuit; floating body; parasitic bipolar turn-on; Circuit simulation; Clocks; Degradation; Latches; Logic circuits; MOSFETs; Medical simulation; Parasitic capacitance; Power supplies; Transconductance;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 1996. Proceedings., 1996 IEEE International
  • Conference_Location
    Sanibel Island, FL
  • ISSN
    1078-621X
  • Print_ISBN
    0-7803-3315-2
  • Type

    conf

  • DOI
    10.1109/SOI.1996.552535
  • Filename
    552535