Thermal effects of die-attach voids location and style on performance of chip level package

Thermal characterisation of chip-scale packaged power devices is crucial to the development of advanced electronic packages for communication and automotive applications. Solder thermal interface materials (STIMs) are often employed in the packaging of power semiconductors to enhance heat dissipation from the chip to the heat spreader. However, voids formation in STIMs impedes heat flow and could result in increase in the chip peak temperature. Three-dimensional finite element analysis is employed to investigate the thermal effects of lead-free solder void percentages, locations and styles on packaged semiconductor device. The thermal resistance of each voiding case is calculated to evaluate the thermal response of the electronic package. The results show that the thermal resistance and peak temperature of electronic package can significantly increase depending on the percentage, location and style of voids. The results would assist packaging and design engineers in the characterisation of the thermal impacts of different solder void patterns.