Effect of Timing Jitter on Sigma Delta ADC for SDR Mobile Receiver

Jitter is the limiting effect for high speed analog-to-digital converters with high resolution and wide digitization bandwidth, which are required in receivers in order to support high data rates. The rapid development of digital wireless system has led to a need of high resolution and high speed analog to digital converter. The performance of a data converter is dependent upon the accuracy and stability of the clock supplied to the circuits. When data converter employ a high sampling rate, clocking issues become magnified and significant distortion can be result. This paper describes minimizing the effect of Timing error such as aperture jitter and clock jitter on the performance of sigma delta ADC Model and Present analytical evaluation of the performance in terms of achievable signal to noise ratio and also draw mean error power spectrum due to aperture jitter and clock jitter.