A unified System C-based framework for simulation, optimization and synthesis of complex systems implementing DSP algorithms

This paper proposes a methodology for fast design-to-synthesis flow. We want to promote an improvement to the currently used methodology, which is based on functional design, refinement, HDL implementation and logic synthesis. Our new approach is based on three principles. One is the choice of a unique modeling language that spans all the needed abstraction levels for hardware system design, from functional verification down to system implementation. The second is the possibility to allow fast system design analysis and exploration avoiding to recompile the model every time the design is changed, by dynamic loading parameters from XML files. Finally we want to support automatic generation of the hardware model from which the final system logic synthesis can be performed.