An ASIC implementation for V-BLAST Detection in 0.35 μm CMOS

The V-BLAST system has been shown to be capable of exploiting the capacity advantage of multiple antenna systems. The square root algorithm for V-BLAST detection is attractive to hardware implementations due to low computational complexity and numerical stability. A low complexity VLSI architecture of the square root algorithm is presented in this paper. The proposed architecture is scalable for various configurations, and implemented in AMIS 0.35 μm CMOS technology for a 4×4 QPSK V-BLAST system. When the received symbol packet length is larger than or equal to 100 bytes, the implemented chip can achieve a maximally possible detection throughput of 128∼160 Mb/s with a maximal clock frequency of 80 MHz.