Evolving sorting networks using genetic programming and the rapidly reconfigurable Xilinx 6216 field-programmable gate array

This paper describes how the massive parallelism of the rapidly reconfigurable Xilinx XC6216 FPCA (in conjunction with Virtual Computing Corporation´s HOT Works board) can be exploited to accelerate the computationally burdensome fitness measurement task of genetic algorithms and genetic programming. This acceleration is accomplished by embodying each individual of the evolving population into hardware in order to perform this time-consuming fitness measurement task. A 16-step sorting network for seven items was evolved that has two fewer steps than the sorting network described in the 1962 O´Connor and Nelson patent on sorting networks (and the same number of steps as a 7-sorter that was devised by Floyd and Knuth (1973) subsequent to the patent and that is now known to be minimal).