DocumentCode :
3239778
Title :
On Increasing Architecture Awareness in Program Optimizations to Bridge the Gap between Peak and Sustained Processor Performance - Matrix-Multiply Revisited
Author :
Parello, D. ; Temam, Olivier ; Verdun, J.
Author_Institution :
HP, France and Paris South University
fYear :
2002
fDate :
16-22 Nov. 2002
Firstpage :
31
Lastpage :
31
Abstract :
As the complexity of processor architectures increases, there is a widening gap between peak processor performance and sustained processor performance so that programs now tend to exploit only a fraction of available performance. While there is a tremendous amount of literature on program optimizations, compiler optimizations lack efficiency because they are plagued by three flaws: (1) they often implicitly use simplified, if not simplistic, models of processor architecture, (2) they usually focus on a single processor component (e.g., cache) and ignore the interactions among multiple components, (3) the most heavily nvestigated components (e.g., caches) sometimes have only a small impact on overall performance. Through the in-depth analysis of a simple program kernel, we want to show that understanding the complex interactions between programs and the numerous processor architecture components is both feasible and critical to design efficient program optimizations.
Keywords :
Bridges; Clocks; Computer architecture; Design optimization; Frequency; Hardware; Kernel; Optimizing compilers; Pipelines; Program processors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Supercomputing, ACM/IEEE 2002 Conference
Conference_Location :
Baltimore, MD, USA
ISSN :
1063-9535
Print_ISBN :
0-7695-1524-X
Type :
conf
DOI :
10.1109/SC.2002.10054
Filename :
1592867
Link To Document :
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