Low Voltage, Low Power, High Linearity, High Speed CMOS Voltage Mode Analog Multiplier

In many applications there is a need to mix the signals of different frequencies or signals of different types, which emphasises the use of mixers or multipliers for different RF applications. In this paper, "CMOS analog multiplier, with less number of transistors which can operate at high frequencies with low power and high linearity" is proposed. The proposed multiplier works on the basis of parallel connected MOS operation circuit. The power consumption is about 40 ¿W. The circuit will work properly from 0.5 V-1.8 V supply voltage and the results for input of 1 volt are presented here. The cut off frequency is about 4 THz, and the simulations results presented here are up to 10 GHz. The THD value for different voltage and frequency settings is in the range of 0.085%-2%. In the proposed architecture the linearity error is very less. The circuit is implemented using 180 nm-tsmc mosis level-49 model and simulated in HSPICE simulator and layout is designed using Tanner EDA L-Edit.