Title :
Low Power Quaternary CMOS Circuit Design
Author :
Madurwar ; Dakhole, P.K.
Author_Institution :
Dept. of Electron. & Commun. Eng., Y.C. Coll. of Eng., Nagpur, India
Abstract :
In this paper voltage mode quaternary circuits are introduced. The quaternary circuits are encoder and decoder circuit, half and full adder circuit. Quaternary operators and elements which are used in the implementation of encoder and decoder circuits, half and full adder are also presented. The set of operators are logical sum, logical product, level up, level down, level conversion operator. Quaternary element is inverter based unit which is also presented. These circuits use two kinds of transistors that is enhancement- mode and depletion-mode transistors. Proposed circuits are static and operate in voltage mode. There is no static dissipation. All these circuits are VLSI implementable and do not use clocking. Simulation results of the introduced quaternary voltage-mode circuit, using SPICE level 3, 1.5 um technology shows higher speed and better performance than existing one.
Keywords :
CMOS integrated circuits; VLSI; adders; invertors; low-power electronics; transistors; SPICE level 3; VLSI implementation; decoder circuit; depletion-mode transistors; encoder circuit; enhancement-mode transistors; full adder circuit; half adder circuit; inverter based unit; level conversion operator; level down; level up; logical product; logical sum; low power quaternary CMOS circuit design; size 1.5 mum; static dissipation; voltage mode quaternary circuits; Adders; Circuit simulation; Circuit synthesis; Clocks; Decoding; Inverters; Logic devices; Power engineering and energy; Very large scale integration; Voltage;
Conference_Titel :
Emerging Trends in Engineering and Technology (ICETET), 2009 2nd International Conference on
Conference_Location :
Nagpur
Print_ISBN :
978-1-4244-5250-7
Electronic_ISBN :
978-0-7695-3884-6
DOI :
10.1109/ICETET.2009.140
