DocumentCode :
3240378
Title :
LALM: a logic-aware layout methodology to enhance the noise immunity of domino circuits
Author :
Im, Yonghee ; Roy, Kaushik
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear :
2003
fDate :
20-21 Feb. 2003
Firstpage :
45
Lastpage :
52
Abstract :
The circuit performance is increasingly affected by signal integrity as cross-talk becomes more significant with scaling down of feature sizes. Many attempts have been made to improve noise immunity, but all require the sacrifice of speed as a tradeoff. In some circuits, P/G network is used as shielding wires to avoid cross-talk while maintaining the desired speed, but the use of the network is inherently restricted by electromigration, IR drop, Ldi/dt noise, etc. We propose a novel methodology at to enhance the noise immunity of domino circuits by reordering transistors as well as interconnects based on the functionality of the circuit. To the best of our knowledge, it is the first attempt to use the functionality of a circuit for the purpose of noise immunity enhancement. The methodology, named "Logic-Aware Layout Methodology" (LALM), uses several techniques that can be used to improve the signal integrity of domino circuits. Experimental results show that LALM is simple to apply yet useful in improving the noise immunity of domino circuits.
Keywords :
crosstalk; integrated circuit noise; integrated logic circuits; logic design; LALM; circuit functionality; crosstalk; domino circuit; logic-aware layout methodology; net ordering; noise immunity; signal integrity; transistor ordering; Circuit noise; Circuit optimization; Coupling circuits; Crosstalk; Intelligent networks; Logic design; MOSFETs; Semiconductor device noise; Subthreshold current; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN :
0-7695-1904-0
Type :
conf
DOI :
10.1109/ISVLSI.2003.1183352
Filename :
1183352
Link To Document :
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