A fine-grain Phased Logic CPU

Author

Reese, Robert B. ; Thornton, Mitchell A. ; Traver, Cherrice

Author_Institution

Mississippi State Univ., MS, USA

fYear

2003

fDate

20-21 Feb. 2003

Firstpage

70

Lastpage

79

Abstract

A five-stage pipelined CPU based on the MIPs ISA is mapped to a self-timed logic family known as Phased Logic (PL). The mapping is performed automatically from a netlist of D-Flip-Flops and 4-input Lookup Tables (LUT4s) to a netlist of Phased Logic gates. Each PL gate implements a 4-input Lookup Table in addition to control logic required for the PL control scheme. PL offers a speedup technique known as Early Evaluation that can be used to boost performance at the cost of additional PL gates. Several different PL gate-level implementations are produced to explore different architectural tradeoffs using early evaluation. Simulations run for five benchmark programs show an average speedup of 1.48 over the clocked netlist at the cost of 17% additional PL gates.

Keywords

flip-flops; logic design; logic gates; microprocessor chips; pipeline processing; table lookup; D-flip-flop; Early Evaluation; control logic; fine-grain Phased Logic CPU; logic gate; lookup table; netlist mapping; pipelined MIPs ISA; self-timed logic design; Application specific integrated circuits; Automatic control; Clocks; Costs; Design methodology; Logic design; Logic devices; Programmable logic arrays; Programmable logic devices; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on

Print_ISBN

0-7695-1904-0

Type

conf

DOI

10.1109/ISVLSI.2003.1183355

Filename

1183355