• DocumentCode
    3240450
  • Title

    A processor-time-minimal schedule for 3D rectilinear mesh algorithms

  • Author

    Scheiman, Chris ; Cappello, Peter

  • Author_Institution
    Dept. of Comput. Sci., California Univ., Santa Barbara, CA, USA
  • fYear
    1995
  • fDate
    24-26 Jul 1995
  • Firstpage
    26
  • Lastpage
    33
  • Abstract
    The paper, using a directed acyclic graph (dag) model of algorithms, investigates precedence constrained multiprocessor schedules for the nx×ny×nz directed rectilinear mesh. Its completion requires at least nx+ny +nz-2 multiprocessor steps. Time-minimal multiprocessor schedules that use as few processors as possible are called processor-time-minimal. Lower bounds are shown for the nx×ny×nz directed mesh, and these bounds are shown to be exact by constructing a processor-time-minimal multiprocessor schedule that can be realized on a systolic array whose topology is either a two dimensional mesh or skewed cylinder. The contribution of this paper is two-fold: It generalizes the previous work on cubical mesh algorithms, and it presents a more elegant mathematical method for deriving processor-time lower bounds for such problems
  • Keywords
    mesh generation; parallel algorithms; processor scheduling; 3D rectilinear mesh algorithms; directed acyclic graph; precedence constrained multiprocessor schedules; processor-time-minimal; processor-time-minimal schedule; skewed cylinder; systolic array; Computer science; Gaussian processes; Labeling; Parallel processing; Processor scheduling; Scheduling algorithm; Systolic arrays; Topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application Specific Array Processors, 1995. Proceedings. International Conference on
  • Conference_Location
    Strasbourg
  • ISSN
    1063-6862
  • Print_ISBN
    0-8186-7109-2
  • Type

    conf

  • DOI
    10.1109/ASAP.1995.522902
  • Filename
    522902