Title :
Architecture, memory and interface technology integration of an industrial/ academic configurable system-on-chip (CSoC)
Author :
Becker, Jurgen ; Vorbach, Martin
Author_Institution :
Karlsruhe Univ., Germany
Abstract :
This paper describes the actual status and results of a dynamically configurable system-on-chip (CSoC) integration, consisting of a SPAR C-compatible LEON processor-core, a commercial coarse-grain XPP-array of suitable size from PACT XPP Technologies AG, and application-tailored global/local memory topology with efficient Amba-based communication interfaces. The given adaptive architecture is synthesized within an industrial/academic SoC project onto 0.18 and 0.13 μm UMC CMOS technologies at Universitaet Karlsruhe (TH). Due to exponentially increasing CMOS mask costs, essential aspects for the industry are now adaptivity of SoCs, which can be realized by integrating reconfigurable re-usable hardware parts on different granularities into configurable systems-on-chip (CSoCs).
Keywords :
CMOS digital integrated circuits; integrated circuit design; logic design; memory architecture; reconfigurable architectures; system buses; system-on-chip; 0.13 micron; 0.18 micron; CMOS mask costs; CSoC architecture; PAE; SPAR C-compatible LEON processor core; SoC adaptivity; adaptive architecture; coarse-grain XPP-array; communication interfaces; dynamically configurable CSoC; global/local memory topology; industrial/academic configurable system-on-chip; interface technology; processing array elements; reconfigurable re-usable hardware granularity; Application specific integrated circuits; Bridges; Computer Society; Computer architecture; Hardware; Master-slave; Random access memory; Read-write memory; System-on-a-chip; Very large scale integration;
Conference_Titel :
VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN :
0-7695-1904-0
DOI :
10.1109/ISVLSI.2003.1183360
