Architectures and integrated circuits for real time vector quantization of images

An architecture for implementing pruned tree search vector quantization (VQ) which has a performance close to the optimal rate distortion bound is presented. A layout design is also presented to verify the feasibility of such an implementation. The chip has been designed as a slave processor which can implement binary, non-binary and pruned tree search VQ algorithms which allow near optimal performance in a mean square error sense while still permitting real time VQ codevectors and external control signals that direct the search. The chip outputs the index of the codevector that best approximates the input in a mean square error sense. The input source and codevectors have a wordlength of 8 bits each. An internal wordlength of 24 bits allows a maximum of 256 pixels per vector. The layout has been generated using a 1.2-μ library and is 5.76 mm×6.6 mm. Critical path simulation with SPICE indicates a maximum clock rate of 40 MHz