Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices

Advanced MOSFETs such as strained silicon (SS) devices have emerged as critical enablers to keep Moore´s law on track for sub-100 nm technologies. Use of strained silicon devices provides performance improvement equivalent to use of next generation devices, without actually requiring scaling. Traditionally, the research in the field of SS has been focussed on device modeling and process characterization. Recently, the dependence of mobility of a SS MOSFET device on its poly-to-poly distance has been reported. In this work, we propose a new methodology to exploit this dependence to achieve cycle time reduction of a design at the layout level. To the best of our knowledge, this is the first research work to tackle timing closure by layout modifications using active area dependent mobility of SS devices. Our methodology shows consistent improvement for benchmark designs mapped onto various 90 nm commercial standard cell libraries. This work enables reduction of cycle time by as much as 6.31% (and on an average 5.25%) very late in the design closure cycle without requiring any optimization iterations.