DocumentCode
3240661
Title
VLSI implementation of an image compression algorithm with a new bit rate control capability
Author
Razavi, Abbas ; Adar, Rutie ; Shenberg, Isaac ; Retter, Rafi ; Friedlander, Rami
Author_Institution
Zoran Corp., Santa Clara, CA, USA
Volume
5
fYear
1992
fDate
23-26 Mar 1992
Firstpage
669
Abstract
An image compression algorithm with a new bit rate control capability is presented. The bit rate control technique is developed for use in conjunction with the JPEG baseline image compression algorithm. The new method is an extension of the previously developed algorithm which is implemented in the Zoran 031 image compression chip set. The chip set comprises a discrete cosine transform (DCT) processor and an image compression coder/decoder. Both methods and the chip set are discussed in detail
Keywords
VLSI; data compression; discrete cosine transforms; image coding; JPEG baseline image compression algorithm; Zoran 031 image compression chip set; bit rate control capability; coder/decoder; discrete cosine transform; image compression algorithm; Bit rate; Block codes; Decoding; Discrete cosine transforms; Image coding; Image generation; Image storage; Pulse modulation; Quantization; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, 1992. ICASSP-92., 1992 IEEE International Conference on
Conference_Location
San Francisco, CA
ISSN
1520-6149
Print_ISBN
0-7803-0532-9
Type
conf
DOI
10.1109/ICASSP.1992.226507
Filename
226507
Link To Document