Title :
The VLSI design and implementation of the array processors of a multilayer vision system architecture
Author :
Saha, B. ; Mertoguno, J.S. ; Bourbakis, N.G.
Author_Institution :
Dept. of Electr. Eng., Binghamton Univ., NY, USA
Abstract :
This paper describes the VLSI design and simulation of the lower layer processors of the KYDON vision system. KYDON is a completely autonomous, hierarchical, multilayered image understanding system. The VLSI design of the individual components as well as the timing simulation results of the processor array have been presented. The system runs at 50 MHz and promises a high processing rate of 300 image frames/sec
Keywords :
VLSI; computer vision; digital simulation; parallel processing; KYDON vision system; VLSI design; array processors; multilayer vision system architecture; multilayered image understanding system; timing simulation; Computational modeling; Computer vision; Coprocessors; Image recognition; Machine vision; Nonhomogeneous media; Pattern recognition; Systolic arrays; Timing; Very large scale integration;
Conference_Titel :
Application Specific Array Processors, 1995. Proceedings. International Conference on
Conference_Location :
Strasbourg
Print_ISBN :
0-8186-7109-2
DOI :
10.1109/ASAP.1995.522913
