Accurate and efficient extraction of interconnect circuits for full-chip timing analysis

As integrated circuit technology migrates into deep submicron geometries, interconnect plays a larger role in determining circuit performance. To correctly model the interconnect in these circuits, RC parasitic effects must be accurately characterized. Pre-layout timing analysis that uses estimated wire lengths and statistical resistance and capacitance values can no longer ensure correct timing, especially for high performance designs (clock speeds faster than 70 MHz). Even post-layout timing analysis, which uses actual wire lengths but typically uses statistical resistance and capacitance values, is usually inadequate to predict the timing actually realized. While pre-layout timing analysis will continue to estimate basic timing relationships, post-layout timing analysis which incorporates actual resistance and capacitance values will need to become a standard part of the IC design flow. This need for greater precision presents a real challenge: designers of deep submicron circuits need an accurate solution that can manage the large designs and volumes of data and provide results within reasonable computation times. Solutions which can provide extreme accuracy for very small designs become cumbersome and unrealistic when applied to a full chip. This paper addresses the types of tools which are available to meet this challenge and suggests techniques to be used by designers to maximize the accuracy of the parasitic extraction while minimizing the time and resources that such accuracy demands