Title :
A design tool for the specification and the simulation of array processors architectures application to image processing: the extraction of regions of interests
Author :
Ramstein, G. ; Deforges, O. ; Bakowski, P.
Author_Institution :
SEI, IRESTE, Nantes, France
Abstract :
This paper deals with a CAD tool dedicated to the design and the simulation of specific array processor architectures. These architectures are described into a specific notation which includes major characteristics of the VHDL syntax. This language provides a very concise and legible means to specify array processors. A preprocessor generates full standard VHDL code describing the behavior of the designed architecture. An original application to image processing is given: the design of a specific architecture for the extraction of regions of interests
Keywords :
circuit analysis computing; hardware description languages; image processing; parallel architectures; CAD tool; VHDL syntax; array processors architectures; design tool; image processing; preprocessor; simulation; specification; Code standards; Design automation; Design methodology; Difference equations; Digital signal processing; Image processing; Object oriented modeling; Silicon compiler; Synthesizers; Transforms;
Conference_Titel :
Application Specific Array Processors, 1995. Proceedings. International Conference on
Conference_Location :
Strasbourg
Print_ISBN :
0-8186-7109-2
DOI :
10.1109/ASAP.1995.522936
