DocumentCode :
3241386
Title :
ISP, JTAG and more for the MAX architecture
Author :
Abu-Lebdeh, Ziad M.
fYear :
1995
fDate :
7-9 Nov. 1995
Firstpage :
200
Abstract :
Flexibility, ease of use, and exceptional speed have been the hallmarks of Altera´s MAX devices from their inception. A new set of features and functionality is being brought to this successful architecture by two new device families: MAX 9000 and MAX 7000S. In addition to the popular features offered by the existing MAX 7000 devices, the primary enhancements that these two families provide are: In-System Programmability (ISP) and JTAG Boundary-Scan Test capability. MAX 7000S family includes device densities up to 5000 usable gates and are completely pin, function, and programming file compatible with existing MAX 7000 and MAX 7000E devices. MAX 9000 devices range from 6,000 to 12,000 usable gates and are therefore the highest density Erasable Programmable Logic Devices (EPLDs) offering ISP capability. In addition to ISP and JTAG, MAX 9000 and MAX 7000S devices include a host of other new features, which are also described
Keywords :
Clocks; Design engineering; Electronics packaging; Logic design; Logic devices; Logic functions; Macrocell networks; Programmable logic arrays; Service oriented architecture; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
WESCON/'95. Conference record. 'Microelectronics Communications Technology Producing Quality Products Mobile and Portable Power Emerging Technologies'
Conference_Location :
San Francisco, CA, USA
ISSN :
1095-791X
Print_ISBN :
0-7803-2636-9
Type :
conf
DOI :
10.1109/WESCON.1995.485277
Filename :
485277
Link To Document :
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