DocumentCode
3241466
Title
The Totem neurochip: an FPGA implementation
Author
Avogadro, M. ; Bera, M. ; Danese, G. ; Leporati, F. ; Spelgatti, A.
Author_Institution
Dipt. di Inf. e Sistemistica, Pavia Univ., Italy
fYear
2004
fDate
18-21 Dec. 2004
Firstpage
461
Lastpage
464
Abstract
In this paper we present the implementation of a successful neurochip, the TotemNC3003 Twinchip by Neuricam, on an FPGA based board lodging the last generation Stratix device from Altera. We already evaluated the performance of the chip in typical neuronal applications, showing that it can outperform a PC, due also to the reactive tabu search algorithm it implements during training and generalising phases. Now, aim of the project is to add a further acceleration degree, by employing a technology which allows to fully integrate the neural algorithm straight onto the hardware and to modify the chip architecture for a more efficient implementation of the neural elaboration.
Keywords
field programmable gate arrays; multiprocessing systems; neural chips; real-time systems; reconfigurable architectures; FPGA implementation; Totem neurochip; multiprocessing; neural network; real time system; reconfigurable architectures; Acceleration; Computer aided instruction; Computer networks; Computer peripherals; Concurrent computing; Data buses; Electronic mail; Field programmable gate arrays; Hardware; Neural networks;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing and Information Technology, 2004. Proceedings of the Fourth IEEE International Symposium on
Print_ISBN
0-7803-8689-2
Type
conf
DOI
10.1109/ISSPIT.2004.1433818
Filename
1433818
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