Author :
Chen, C.-T. ; Britton, Barry K.
Abstract :
The gate density for the Field Programmable gate array (FPGA) has grown rapidly for the past year. Today 40,000 usable gates is a reality and the density will continue to grow in the near future. Unfortunately, the power consumption also grows with the gate density. This coupled with the 3.3 V system applications such as PCMCIA calls for the need of an FPGA in 3.3 V. This paper describes the design challenges in implementing the 3.3 V Optimized Reconfigurable Cell Array (ORCA) FPGAs known as the 2T series
Keywords :
CMOS technology; Clocks; Design optimization; Energy consumption; Field programmable gate arrays; Microelectronics; Power supplies; Signal design; Timing; Voltage;
Conference_Titel :
WESCON/'95. Conference record. 'Microelectronics Communications Technology Producing Quality Products Mobile and Portable Power Emerging Technologies'
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-2636-9
DOI :
10.1109/WESCON.1995.485281