A method for redesign for testability at the RT level

Author

Harmanani, Haidar ; Harfoush, Salam

Author_Institution

Dept. of Comput. Eng. & Sci., Lebanese American Univ., Byblos, Lebanon

Volume

1

fYear

1998

fDate

24-28 May 1998

Firstpage

157

Abstract

A new method of redesign for testability at the register-transfer level (RTL) is proposed. The method identifies hard to test parts of a an RTL design synthesized either manually or automatically using high-level synthesis tools. The design is modified by inserting additional test registers followed by a test selection process. During the selection process, two test metrics are used in order to minimize test overhead. Finally, test scheduling is performed so that to minimize the overall test time and the number of test sessions. The system outputs a VHDL description of a testable data path along with a test plan

Keywords

VLSI; built-in self test; design for testability; hardware description languages; high level synthesis; integrated circuit design; shift registers; BIST; RT level; RTL design; VHDL description; VLSI circuitry; high-level synthesis tools; redesign method; register-transfer level; test overhead minimisation; test plan; test registers; test scheduling; test selection process; test time; testability; testable data path; Automatic testing; Built-in self-test; Circuit testing; Design for testability; High level synthesis; Logic testing; Pattern analysis; Registers; Scheduling; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 1998. IEEE Canadian Conference on

Conference_Location

Waterloo, Ont.

ISSN

0840-7789

Print_ISBN

0-7803-4314-X

Type

conf

DOI

10.1109/CCECE.1998.682706

Filename

682706