Task scheduling in the Georgia Tech digital signal multiprocessor

The use of realistic structural and behavioral level descriptions of digital signal multiprocessors to find rate optimal and processor optimal schedules for implementation on multiprocessor digital signal processor (DSP) systems is addressed. Unlike previous work, the digital signal multiprocessor compiler (DSMP-C1) explicitly considers the location of operands, the number of accumulators and registers, the size of on-chip and external memories, the size of communication buffers, and inter-processor communications. The algorithm implicitly retimes and pipelines the flow graph and generates overlapping PSSIMD schedules that are both rate and processor optimal. When compared to previously published scheduling algorithms, the DSMP-C1 algorithm produces significantly shorter iteration periods