DocumentCode
3241630
Title
Incremental Criticality and Yield Gradients
Author
Xiong, Jinjun ; Zolotov, Vladimir ; Visweswariah, Chandu
Author_Institution
Thomas J. Watson Res. Center, IBM, Yorktown Heights, NY
fYear
2008
fDate
10-14 March 2008
Firstpage
1130
Lastpage
1135
Abstract
Criticality and yield gradients are two crucial diagnostic metrics obtained from statistical static timing analysis (SSTA). They provide valuable information to guide timing optimization and timing- driven physical synthesis. Existing work in the literature, however, computes both metrics in a non-incremental manner, i.e., after one or more changes are made in a previously-timed circuit, both metrics need to be recomputed from scratch, which is obviously undesirable for optimizing large circuits. The major contribution of this paper is to propose two novel techniques to compute both criticality and yield gradients efficiently and incrementally. In addition, while node and edge criticalities are addressed in the literature, this paper for the first time describes a technique to compute path criticalities. To further improve algorithmic efficiency, this paper also proposes a novel technique to update "chip slack" incrementally. Numerical results show our methods to be over two orders of magnitude faster than previous work.
Keywords
integrated circuit yield; statistical analysis; timing; algorithmic efficiency; chip slack; edge criticalities; incremental criticality; node criticalities; path criticalities; statistical static timing analysis; yield gradients; CMOS process; CMOS technology; Circuit optimization; Circuit synthesis; Delay; Design optimization; Digital circuits; Manufacturing processes; Probability; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 2008. DATE '08
Conference_Location
Munich
Print_ISBN
978-3-9810801-3-1
Electronic_ISBN
978-3-9810801-4-8
Type
conf
DOI
10.1109/DATE.2008.4484830
Filename
4484830
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