An integrated flow for ASIC designs with FPGA prototyping-a designer´s perspective

Issues in FPGA to ASIC conversions, such as netlist translation, re-use of simulation vectors, static timing comparisons and physical design are analyzed. Some techniques to address related problems are discussed. An integrated approach for ASIC design with FPGA prototyping, that aims to minimize the risk and effort involved in retargeting, is then presented