Robust design of 0.18 μm ASIC MOSFETs using Taguchi method with TCAD

Author

Kamohara, Shiro ; Kawakami, M. ; Kosaka, E. ; Ito, F. ; Okuyama, K. ; Ohji, Y.

Author_Institution

Semicond. & Integrated Circuits, Hitachi Ltd., Tokyo, Japan

fYear

2001

fDate

2001

Firstpage

21

Lastpage

24

Abstract

Taguchi method has been applied to optimize the 0.18 μm ASIC MOSFETs. We proposed a suitable condition of MOSFETs to achieve the target of Vt variance, which is determined from the target of the yield and Idsat, which is determined from the demand of customers. When performing TCAD simulation, we have compounded the noise factors to reduce the number of the simulations. Based on Taguchi method, we have successfully reduced the Vt variance by about half from the original device (i.e. increased the yield) and increased Idsat to meet the target in the real product

Keywords

MOS integrated circuits; MOSFET; Taguchi methods; VLSI; application specific integrated circuits; circuit optimisation; integrated circuit design; integrated circuit noise; integrated circuit yield; technology CAD (electronics); 0.18 micron; ASIC; IC design; MOSFETs; TCAD; Taguchi method; VLSI; circuit optimisation; noise factors; yield; Application specific integrated circuits; Calibration; Design methodology; MOSFETs; Mass production; Noise reduction; Optimization methods; Research and development; Robustness; Stability;

fLanguage

English

Publisher

ieee

Conference_Titel

Statistical Methodology, IEEE International Workshop on, 2001 6yh.

Conference_Location

Kyoto

Print_ISBN

0-7803-6688-3

Type

conf

DOI

10.1109/IWSTM.2001.933818

Filename

933818