Map, place and route: the key to high-density PLD implementation

Development tools for high-density programmable logic devices (PLDs) must be capable of implementing complex logic designs on an engineer´s desktop PC or workstation, and deliver the ease-of-design and fast time-to-market benefits that have popularized PLD technology. Given the complexity of modern Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate Arrays (FPGAs), effective; highly-automated CPLD and FPGA implementation tools are indispensable for achieving good performance and maximizing logic capacity