Investigation of interfacial delamination for Cu/low k structures during flip-chip packaging

Chip-packaging interaction is becoming a more and more interesting and critical issue during package assembly. Since traditional ILD material, TEOS, is being replaced by much weaker low k materials, packaging is suspected to affect the reliability of Cu/low k interconnects. Packaging induced interfacial delamination along low k material interfaces has been widely observed. Thermal deformation of a package is directly related to the reliability of Cu/low k interconnects located at the chip surface. In this paper, we will first review the experimental techniques for package thermal deformation measurement and interfacial fracture energy measurement for low k interfaces. Then 3D finite element analysis (FEA) based on a multilevel sub-modeling approach in combination with high-resolution moire interferometry is employed to examine the packaging effect on low k interconnect reliability. Packaging induced crack driving forces for low k interface delaminations are obtained. Our research results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low k structures.