Title :
Trace crack in thin CSP molded package and underlying failure mechanism
Author :
Carpenter, Burton J. ; Yuan, Yuan
Author_Institution :
Semicond. Product Sector, Motorola, Austin, TX, USA
Abstract :
Trace cracks were observed during the qualification of a new thin Plastic Ball Grid Array (PBGA) package. These occurred in the substrate during the component level air-to-air temperature cycle (AATC) stress test. There were three aspects to the ensuing investigation: failure analysis (FA), finite element method (FEM) simulation and additional AATC testing to confirm the findings. The FA consistently revealed that the underlying failure mechanism was cracking in the substrate core dielectric material which initiated between the bundles of the glass cloth. These epoxy rich regions in the micro-structure were generally the weakest portions of the composite. Parametric simulation using FEM provided guidance on how to reduce the package core stress, including the selection of packaging materials with optimal properties. This included different molding compound materials, die attach materials, solder-mask materials and substrate core materials. FEM simulation also investigated the impact of design parameters, such as core thickness, die attach layer thickness, trace layer thickness, ratio of die/substrate area, molding compound thickness etc. The investigation suggested the use of a core with multiple layers of fiberglass cloth and tighter knitting patterns to improve the core microstructure. AATC tests were then performed using die size, core material and solder-mask material as the variables. These tests were important to validate the underlying failure mechanism. The final material set selection exceeded the temperature cycle requirement.
Keywords :
ball grid arrays; composite materials; cracks; dielectric materials; failure analysis; finite element analysis; microassembling; moulding; plastic packaging; reliability; solders; FEM simulation; air-air temperature cycle stress test; composite; design parameter impact; die size; die-substrate area ratio; failure analysis; failure mechanism; fiberglass; fiberglass cloth layer; finite element method; microstructure; molding; molding compound thickness; package core stress reduction; packaging materials; parametric simulation; plastic ball grid array; solder-mask material; substrate core dielectric material; trace crack; trace layer thickness; Chip scale packaging; Dielectric materials; Dielectric substrates; Failure analysis; Microassembly; Plastics; Qualifications; Stress; Temperature; Testing;
Conference_Titel :
Thermal and Thermomechanical Phenomena in Electronic Systems, 2004. ITHERM '04. The Ninth Intersociety Conference on
Print_ISBN :
0-7803-8357-5
DOI :
10.1109/ITHERM.2004.1318288