DocumentCode
3241837
Title
Impact of nMOS/pMOS gate length correlation on the accuracy of statistical modeling
Author
Komatsubara, Hirotaka ; Miura, Noriyuki ; Hayashi, Hirokazu ; Mochizuki, Marie ; Rukuda, K. ; Yajima, Tsukasa ; Yoshida, Masahiro ; Wakayama, Keiichi ; Nishitani, Akito ; Nagatomo, Yoshiki
Author_Institution
Oki Electr. Ind. Co. Ltd., Tokyo, Japan
fYear
2001
fDate
2001
Firstpage
47
Lastpage
50
Abstract
In LSI design of modern scaled-down technologies, the statistical model is used to take process variation effects into account. In order to predict device fluctuations in early stages of device development, the TCAD approach of statistical modeling has already been introduced in some reports. But from statistical modelling points of view, prediction accuracy of such TCAD approaches has not been sufficiently discussed. In this paper, statistical distribution of factory-manufactured devices is compared carefully to the prediction of TCAD. It is revealed that there is no serious accuracy problem in statistical model prediction even with economically calibrated TCAD, On the other hand, consideration of nMOS and pMOS gate length correlation is found to be critical to the prediction
Keywords
MOS integrated circuits; integrated circuit manufacture; large scale integration; semiconductor process modelling; statistical analysis; technology CAD (electronics); LSI design; TCAD; factory-manufactured devices; gate length correlation; prediction accuracy; process variation effects; scaled-down technologies; statistical modeling; Calibration; Economic forecasting; Fluctuations; Intrusion detection; Large scale integration; MOS devices; Manufacturing; Predictive models; Production facilities; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Statistical Methodology, IEEE International Workshop on, 2001 6yh.
Conference_Location
Kyoto
Print_ISBN
0-7803-6688-3
Type
conf
DOI
10.1109/IWSTM.2001.933824
Filename
933824
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