A statistical design methodology of a 0.12-μm CMOS device for MPU applications

Author

Fukuda, Tomoyuki ; Honzawa, Atushi ; Wada, Shinichiro ; Mori, Kazutaka ; Kunitomo, Hisaaki ; Sato, Hisako

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

2001

fDate

2001

Firstpage

54

Lastpage

57

Abstract

We designed a 0.12-μm CMOS device using TCAD statistical simulation. We investigated techniques to reduce subthreshold leakage currents (Ioff) without degrading device performance to make IDDQ tests effective for large-scale and high-performance MPUs. Roll-off characteristics of threshold voltages were optimized considering process variations and maximum Ioff limitations. We demonstrated that a device with relatively large roll-off characteristics is superior to a conventional one in terms of MPU operation frequency

Keywords

CMOS digital integrated circuits; circuit simulation; design for testability; integrated circuit design; leakage currents; logic CAD; microprocessor chips; statistical analysis; technology CAD (electronics); 0.12 micron; CMOS device; IDDQ tests; MPU applications; TCAD statistical simulation; operation frequency; process variations; roll-off characteristics; statistical design methodology; subthreshold leakage currents; threshold voltages; Circuit simulation; Design methodology; Frequency; Implants; Impurities; Intrusion detection; Large scale integration; MOS devices; MOSFET circuits; Medical simulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Statistical Methodology, IEEE International Workshop on, 2001 6yh.

Conference_Location

Kyoto

Print_ISBN

0-7803-6688-3

Type

conf

DOI

10.1109/IWSTM.2001.933826

Filename

933826