Rapid prototyping for hardware accelerated elliptic curve public-key cryptosystems

A generator-based design and validation methodology for rapid prototyping of elliptic curve public-key cryptosystem hardware is described. By their very nature, cryptosystems challenge both design and validation. Pure RTL-based synthesis is as unsuitable as high-level synthesis. Instead, a generator program accepts the two main parameters - the key size and the multiplier radix - and creates a highly efficient custom RTL description which is synthesized into a FPGA. This approach benefits the design in that it allows one to effortlessly exploit the available resources on the FPGA for variable requirements of security and performance. It is also advantageous for validation of the correctness of the design as, for small parameter values, the design can be tested exhaustively. Thus, the correctness for large key sizes depends only on the correctness of the generator. Furthermore, deploying FPGAs supports integration of an ASIC realisation of the same algorithm, which boosts performance. By emulating its interface, the ASIC can be accommodated even before fabrication, thus enabling mixed FPGA/ASIC acceleration of elliptic curve cryptosystems