DocumentCode :
3242082
Title :
3D structure design and reliability analysis of wafer level package with bubble-like stress buffer layer
Author :
Lee, Chang-Chun ; Liu, Hsin-Chih ; Yew, Ming-Chih ; Chian, Kuo-Ning
Author_Institution :
Dept. of Power Mech. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume :
2
fYear :
2004
fDate :
1-4 June 2004
Firstpage :
317
Abstract :
With the present trend of multi-function and minimizing of size, the conventional electronic package type no longer meets the requirement of the new-generation products. Consequently, new type packaging, based on the wafer level packages (WLP) and chip scale packages (CSP) technology are being developed to achieve these requirements, as well as long term reliability. Novel wafer-level chip scale packages (WLCSP) with a stress buffer layer and bubble-like plate are proposed in this research to improve the solder joint fatigue life. The thermal stress caused by the coefficient of thermal expansion (CTE) mismatch can be significantly reduced, and the reliability of the WLP could be substantially enhanced by this new design. In order to realize the relationship of the solder joint fatigue life, stress buffer layer and bubble-like plate, a finite element parametric analysis applying software ANSYS® is utilized. The design parameters include the thickness of the stress buffer layer, thickness, bending angle and standoff height of the different types of bubble-like plate. The results of the finite element method (FEM) analysis reveal that the stress buffer layer and bubble-like plate can relax the thermal stresses of solder joints and enhance the package reliability. In addition, the peeling stress between stress buffer layer and two different types of bubble-like plates is discussed, and the stress state of the leadframe is also analyzed in this research. Furthermore, the findings of this research can be used as the guideline for advanced WLCSP design.
Keywords :
adhesion; bending; chip scale packaging; chip-on-board packaging; circuit reliability; failure analysis; fatigue testing; finite element analysis; integrated circuit design; life testing; solders; stress-strain relations; thermal expansion; thermal stresses; 3D structure design; CTE; FEM; bending angle; bubble like stress buffer layer; bubble-like plate; electronic package; finite element parametric analysis; leadframe; package reliability; peeling stress; software ANSYS®; solder joint fatigue life; standoff height; thermal expansion coefficient; thermal stress relaxation; wafer level package; wafer-level chip scale packages; Buffer layers; Chip scale packaging; Electronic packaging thermal management; Electronics packaging; Fatigue; Finite element methods; Soldering; Thermal expansion; Thermal stresses; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Thermal and Thermomechanical Phenomena in Electronic Systems, 2004. ITHERM '04. The Ninth Intersociety Conference on
Print_ISBN :
0-7803-8357-5
Type :
conf
DOI :
10.1109/ITHERM.2004.1318299
Filename :
1318299
Link To Document :
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