Fanout fault analysis for digital logic circuits

Author

Chen, Beyin ; Lee, Chung Len ; Shen, Wen Zen ; Beyin Chen

Author_Institution

Dept. of Electr. Eng., Chung-Hua Polytech. Inst., Hsinchu, Taiwan

fYear

1995

fDate

23-24 Nov. 1995

Firstpage

33

Lastpage

39

Abstract

Conventional fault relationships are mostly restricted to faults at a gate or within a fanout free region. In this paper, we analyze the fault relationships beyond the fanout free region for general digital logic circuits. An improved fault collapsing procedure is proposed and applied to several kinds of combinational benchmark circuits and 31 sequential benchmark circuits to collapsing faults. Improvements of 2-8% for an initial set of target faults of a circuit can be obtained. For some of circuits, the reduction ratio can have up to 20% improvement. This may save a lot of time in test generation and fault simulation processes.

Keywords

combinational circuits; fault diagnosis; logic testing; sequential circuits; combinational benchmark circuits; digital logic circuits; fanout fault analysis; fault collapsing; fault simulation; sequential benchmark circuits; target faults; test generation; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Delay; Fault detection; Labeling; Logic circuits; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1995., Proceedings of the Fourth Asian

Conference_Location

Bangalore, India

Print_ISBN

0-8186-7129-7

Type

conf

DOI

10.1109/ATS.1995.485313

Filename

485313