DocumentCode :
3242329
Title :
A fault location technique and alternate routing in Benes network
Author :
Das, Nabanita ; Dattagupta, Jayasree
Author_Institution :
Electron. Unit, Indian Stat. Inst., Calcutta, India
fYear :
1995
fDate :
23-24 Nov 1995
Firstpage :
71
Lastpage :
77
Abstract :
An NxN Benes network B(n), (n=log2N), being a rearrangeable network, can realize any NxN permutation in a single pass. But even in the presence of a single switch fault in B(n), no NxN permutation can be implemented in one pass, it requires either recirculation through intermediate nodes, or reconfiguration of the system in a degraded mode. We characterize a class C of multiple switch faults in B(n), in the presence of which the network is always capable of realizing any arbitrary NxN permutation P in two passes. By this technique, every source-destination path is set up in a single pass, only the whole set of N source-destination paths of P is partitioned in two subsets and are realized in two successive passes. The novelty of the routing technique lies in the fact that the exact locations of the faults are not important here, only the information of an optimal region of the network containing the faulty switch is sufficient. This feature actually enables us to develop here, very fast and simple procedures for multiple switch fault detection and location as well. In this paper, we have shown that just two one bit test vectors are sufficient to detect and locate all single faults, all double faults and also many cases with 3, 4, 5 and 6 faults. Given a set F of multiple switch faults, we detect and locate its equivalent fault set F´ by the fault location technique presented
Keywords :
fault diagnosis; fault tolerant computing; multistage interconnection networks; network routing; reconfigurable architectures; Benes network; alternate routing; equivalent fault set; exact locations; fault location technique; multiple switch fault detection; multistage interconnection networks; one bit test vectors; rearrangeable network; recirculation; reconfiguration; routing technique; single switch fault; source-destination path; Degradation; Fault detection; Fault location; Fault tolerance; Fault tolerant systems; Intelligent networks; Multiprocessor interconnection networks; Routing; Switches; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium, 1995., Proceedings of the Fourth Asian
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7129-7
Type :
conf
DOI :
10.1109/ATS.1995.485319
Filename :
485319
Link To Document :
بازگشت