Title :
Plasma damage evaluation using matched transistors and determination of damage prevention options
Author :
Ellis, John ; Comeau, Alain R. ; Porter, Richard ; Bossingham, John ; Alestig, Göran
Author_Institution :
Mitel Semicond. Ltd., Plymouth, UK
Abstract :
In this paper, we demonstrate the importance of the interaction between layout and process in reducing the impact of RIE plasma damage. We show that less than optimum layout and a less than optimum process sequence can lead to very severe degradation of device characteristics due to plasma damage, resulting in near zero yielding wafers. Measurements on test transistors can replicate the damage caused and lead to a means of controlling the damage
Keywords :
MOSFET; circuit optimisation; integrated circuit layout; integrated circuit reliability; integrated circuit testing; integrated circuit yield; sputter etching; surface charging; IC layout/process interaction; RIE plasma damage; damage control; damage prevention; damage replication; device characteristics degradation; matched transistors; optimum layout; optimum process sequence; plasma damage; plasma damage evaluation; test transistors; wafer yield; Circuits; Etching; MOS devices; Plasma applications; Plasma devices; Plasma measurements; Plasma properties; Stress; Tunneling; Voltage;
Conference_Titel :
Plasma Process-Induced Damage, 1999 4th International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-9651577-3-3
DOI :
10.1109/PPID.1999.798817
