DocumentCode :
3242353
Title :
Optimal shielding/spacing metrics for low power design
Author :
Arunachalam, Ravishankar ; Acar, Emrah ; Nassif, Sani R.
Author_Institution :
I.B.M. Electron. Design Autom., Austin, TX, USA
fYear :
2003
fDate :
20-21 Feb. 2003
Firstpage :
167
Lastpage :
172
Abstract :
Noise arising from line-to-line coupling is a major problem for deep submicron design, and present technology trends are causing an increase in this type of noise. Common current methods to decrease coupling noise include shielding and buffering, both of which can increase overall power dissipation. An alternative method is spacing, which has the added benefit of improving the manufacturability (i.e. defect insensitivity) of the design. This paper explores the issue of coupling noise reduction, and proposes performance metrics that can be used by the designer to determine which of the alternative methods is best suited for a specific interconnect configuration.
Keywords :
VLSI; integrated circuit design; integrated circuit interconnections; integrated circuit noise; low-power electronics; shielding; coupling noise; deep submicron design; interconnect configuration; line-to-line coupling; low power design; manufacturability; optimal shielding/spacing metrics; performance metrics; Capacitance; Costs; Electronic design automation and methodology; Power dissipation; Routing; Signal design; Silicon; Switches; Timing; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN :
0-7695-1904-0
Type :
conf
DOI :
10.1109/ISVLSI.2003.1183442
Filename :
1183442
Link To Document :
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