Plasma damage during dielectric etch in high density plasma etcher

Author

Tsui, Bing-Yue ; Lin, Shyue-Shyh ; Tsai, Chia-Shone ; Hsia, Chin C.

Author_Institution

Deep Sub-micron Technol. Div., Ind. Technol. Res. Inst., Hsinchu, Taiwan

fYear

1999

fDate

1999

Firstpage

84

Lastpage

87

Abstract

Plasma process induced damage from a high density plasma dielectric etcher was studied comprehensively. PMOS devices are damaged more readily than NMOS devices. Low field gate current is the most sensitive parameter to reflect damage. Latent defects in the form of oxide-traps were observed after back-end-of-line processing. These latent defects result in poor gate oxide integrity under Fowler-Nordheim stress or hot carrier stress. Plasma damage during contact or via hole etch must therefore be considered carefully

Keywords

CMOS integrated circuits; dielectric thin films; electron traps; hole traps; hot carriers; integrated circuit interconnections; integrated circuit reliability; integrated circuit testing; plasma density; plasma materials processing; sputter etching; surface charging; CMOS technology; Fowler-Nordheim stress; NMOS devices; PMOS devices; SiO₂-Si; back-end-of-line processing; contact etch; dielectric etch; gate oxide integrity; high density plasma dielectric etcher; high density plasma etcher; hot carrier stress; latent defects; low field gate current; oxide-traps; plasma damage; plasma process induced damage; via hole etch; Dielectrics; Etching; Hot carriers; MOS devices; Plasma applications; Plasma density; Plasma devices; Plasma materials processing; Plasma measurements; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Plasma Process-Induced Damage, 1999 4th International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-9651577-3-3

Type

conf

DOI

10.1109/PPID.1999.798819

Filename

798819