Fast fault simulation for BIST applications

Author

Kung, Chen-Pin ; Huang, Chun-Jieh ; Lin, Chen-Shang

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

1995

fDate

23-24 Nov 1995

Firstpage

93

Lastpage

99

Abstract

Fault simulation is essential to design a high fault-coverage BIST. The simulation is characterized by combinational fault simulation and signature computation with a large amount of test patterns. In this paper, a fast fault simulator BISTSIM for BIST is developed. For the combinational fault simulation, a novel demand-driven logic simulation algorithm is proposed. Moreover, efficient fault propagation methods are incorporated into BISTSIM. The experimental results show that the proposed fault simulator delivers better performance than FSIM; about 2 to 3 times for circuits with a large number of test patterns. For signature evaluation of MISR to determine the aliasing, two efficient simulation methods, bit-array computation and parallel-pattern sequential simulation, are proposed. The resultant BISTSIM outperforms the fast fault simulator HOPE1.1 with an average speedup ratio of 10

Keywords

VLSI; built-in self test; circuit analysis computing; combinational circuits; digital simulation; integrated circuit testing; logic testing; BIST applications; BISTSIM; MISR; VLSI; aliasing; bit-array computation; combinational fault simulation; demand-driven logic simulation algorithm; fault propagation methods; parallel-pattern sequential simulation; signature computation; speedup ratio; test patterns; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Costs; Electrical fault detection; Fault detection; Hardware; Logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1995., Proceedings of the Fourth Asian

Conference_Location

Bangalore

Print_ISBN

0-8186-7129-7

Type

conf

DOI

10.1109/ATS.1995.485322

Filename

485322