Hardware-accelerated concurrent fault simulation: eventflow computing versus dataflow computing

MuSiC, the highly-parallel Munich Simulation Computer, represents an approach for hardware-accelerated logic simulation by applying concepts developed for dataflow architectures to high-speed simulation of digital systems. This approach exploiting parallelism inherent in a design is most efficient. In comparison to two different dataflow computation schemes and their hardware-accelerated implementations, this paper shows that the strategy of compiler-driven simulation can be combined with the concept of event-(activity)-directed simulation (selective trace simulation) not only for logic simulation but also for concurrent fault simulation. Experiments indicate that there is a performance advantage of eventflow computing over the algorithmically simpler dataflow computing schemes but the advantage is limited, since dataflow computing performance of a MuSiC version with 256 Processing Units already is in the range of 10⁷ to 10⁸ test-vectors times gates evaluated per second